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8-/16-Channel, 3 V/5 V, Serial Input, SingleSupply, 12-/14-Bit Voltage Output DACs AD5390/AD5391/AD5392
FEATURES
AD5390: 16-channel, 14-bit voltage output DAC AD5391: 16-channel, 12-bit voltage output DAC AD5392: 8-channel, 14-bit voltage output DAC Guaranteed monotonic INL: 1 LSB max (AD5391) 3 LSB max (AD5390-5/AD5392-5) 4 LSB max (AD5390-3/AD5392-3) On-chip 1.25 V/2.5 V, 10 ppm/C reference Temperature range: -40C to +85C Rail-to-rail output amplifier Power-down mode Package types: 64-lead LFCSP (9 mm x 9 mm) 52-lead LQFP (10 mm x 10 mm) User interfaces: Serial SPI(R)-, QSPITM-, MICROWIRETM-, and DSP-compatible (featuring data readback) I2C(R)-compatible interface
INTEGRATED FUNCTIONS
Channel monitor Simultaneous output update via LDAC Clear function to user-programmable code Amplifier boost mode to optimize slew rate User-programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor
APPLICATIONS
Instrumentation and industrial control Power amplifier control Level setting (ATE) Control systems Microelectromechanical systems (MEMs) Variable optical attenuators (VOAs) Optical transceivers (MSA 300, XFP)
FUNCTIONAL BLOCK DIAGRAM
DVDD (x2) DGND (x2) AVDD (x2) AGND (x2) DAC_GND (x2) REF_GND REFOUT/REFIN SIGNAL_GND (x2)
AD5390
1.25V/2.5V REFERENCE
SPI/I2C DCEN/AD1
14
INPUT REG 0 14
14
14
DAC REG 0
14 DAC 0 VOUT 0
m REG0 c REG0 14 14 DAC REG 1 14 DAC 1 VOUT 1 VOUT 2 R R VOUT 3 VOUT 4 R R
DIN/SDA SCLK/SCL SYNC/AD0 SDO INTERFACE CONTROL LOGIC
STATE MACHINE AND CONTROL LOGIC
14
14
INPUT REG 1 14 14
m REG1 c REG1
BUSY PD CLR RESET POWER-ON RESET 14 INPUT REG 6 14 14 14 14 DAC REG 6 14
DAC 6
VOUT 5 VOUT 6
m REG6 c REG6 14 14 DAC REG 7 14 DAC 7 VOUT 7 VOUT 8 R R
VIN0
VIN15
14
INPUT REG 7 14
MON_IN1 MUX MON_IN2
m REG7 c REG7
14
x2
LDAC
R
R VOUT 15
03773-0-001
MON_OUT
Figure 1. Rev. A
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AD5390/AD5391/AD5392 TABLE OF CONTENTS
General Description ......................................................................... 3 AD5390-5/AD5391-5/AD5392-5 Specifications.......................... 4 AD5390-5/AD5391-5/AD5392-5 AC Characteristics................. 6 AD5390-3/AD5391-3/AD5392-3 Specifications.......................... 7 AD5390-3/AD5391-3/AD5392-3 AC Characteristics................. 9 Timing Characteristics: Serial SPI-, QSPI-, Microwire-, and DSP-Compatible Interface............................................................. 10 Timing Characteristics: I2C Serial Interface................................ 13 Absolute Maximum Ratings.......................................................... 14 ESD Caution................................................................................ 14 Pin Configuraton and Function Descriptions ............................ 15 Power-On Reset.......................................................................... 35 Terminology .................................................................................... 18 Power-Down ............................................................................... 35 Typical Performance Characteristics ........................................... 19 Microprocessor Interfacing....................................................... 35 Functional Description .................................................................. 23 Application Information................................................................ 37 DAC Architecture--General..................................................... 23 Power Supply Decoupling ......................................................... 37 Data Decoding--AD5390/AD5392 ......................................... 24 Typical Configuration Circuit .................................................. 37 Data Decoding--AD5391 ......................................................... 24 AD539x Monitor Function ....................................................... 38 Interfaces.......................................................................................... 25 Toggle Mode Function............................................................... 38 DSP-, SPI-, and MICROWIRE-Compatible Serial Interface 25 Thermal Monitor Function....................................................... 38 I2C Serial Interface.......................................................................... 27 Outline Dimensions ....................................................................... 40 I2C Data Transfer ........................................................................ 27 Ordering Guide .......................................................................... 41 START and STOP Conditions .................................................. 27 Repeated START Condition...................................................... 27 Acknowledge Bit (ACK) ............................................................ 27 I2C Write Operation ....................................................................... 28 4-Byte Mode................................................................................ 28 3-Byte Mode................................................................................ 29 2-Byte Mode................................................................................ 30 AD539x On-Chip Special Function Registers........................ 31 Control Register Write............................................................... 33 Hardware Functions....................................................................... 35 Reset Function ............................................................................ 35 Asynchronous Clear Function.................................................. 35 BUSY and LDAC Functions...................................................... 35
REVISION HISTORY
10/04: Data Sheet Changed from Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 6 Changes to Table 4............................................................................ 7 Changes to Figure 36...................................................................... 35 Changes to Figure 37...................................................................... 36 Changes to Figure 38...................................................................... 36 Changes to Ordering Guide .......................................................... 41 4/04--Revision 0: Initial Version
Rev. A | Page 2 of 44
AD5390/AD5391/AD5392 GENERAL DESCRIPTION
The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC. Devices are available both in 64-lead LFCSP and 52-lead LQFP packages. All channels have an on-chip output amplifier with rail-to-rail operation. All devices include an internal 1.25/2.5 V, 10 ppm/C reference, an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring, and an output amplifier boost mode that optimizes the output amplifier slew rate. The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible Table 1. Additional High Channel Count, Low Voltage, Single-Supply DACs in Portfolio
Model AD5380BST-5 AD5380BST-3 AD5384BBC-5 AD5384BBC-3 AD5381BST-5 AD5381BST-3 AD5382BST-5 AD5382BST-3 AD5383BST-5 AD5383BST-3 Resolution 14 Bits 14 Bits 14 Bits 14 Bits 12 Bits 12 Bits 14 Bits 14 Bits 12 Bits 12 Bits AVDD Range 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V 4.5 V to 5.5 V 2.7 V to 3.6 V Output Channels 40 40 40 40 40 40 32 32 32 32 Linearity Error (LSB) 4 4 4 4 1 1 4 4 1 1 Package Description 100-Lead LQFP 100-Lead LQFP 100-Lead CSPBGA 100-Lead CSPBGA 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP Package Option ST-100 ST-100 BC-100 BC-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100
with SPI, QSPI, MICROWIRE, and DSP interface standards and an I2C-compatible interface supporting a 400 kHz data transfer rate. An input register followed by a DAC register provides doublebuffering, allowing DAC outputs to be updated independently or simultaneously using the LDAC input. Each channel has a programmable gain and offset adjust register, letting the user fully calibrate any DAC channel. Power consumption is typically 0.25 mA per channel.
Rev. A | Page 3 of 44
AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient2 DC Crosstalk2 REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output 3 AD5390-51 AD5392-51 14 3 -1/+2 4 4 5 0.024 0.06 2 0.5 AD5391-51 Unit 12 1 1 4 4 5 0.024 0.06 2 0.5 Bits LSB max LSB max mV max mV max V/C typ % FSR max % FSR max ppm FSR/C typ LSB max Test Conditions/Comments
Guaranteed monotonic over temperature. Measured at code 32 in the linear region. At 25C TMIN to TMAX.
2.5 1 1 1 V to AVDD/2
2.5 1 1 1 V to AVDD/2
V M min A max V min/max
1% for specified performance, AVDD = 2 x REFIN + 50 mV. Typically 100 M. Typically 30 nA.
Output Voltage Reference TC Output Impedance OUTPUT CHARACTERISTICS2 Output Voltage Range4 Short-Circuit Current Load Current Capacitive Load Stability RL = RL = 5 k DC Output Impedance MONITOR OUTPUT PIN Output Impedance Three-State Leakage Current LOGIC INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance
2.495/2.505 1.22/1.28 10 15 2.2 0/AVDD 40 1 200 1,000 0.5 500 100 2 0.8 10 10
2.495/2.505 1.22/1.28 10 15 2.2 0/AVDD 40 1 200 1,000 0.5 500 100 2 0.8 10 10
V min/max V min/max ppm max ppm max k typ V min/max mA max mA max pF max pF max max typ nA typ
Enabled via internal/external bit in control register. REF select bit in control register selects the reference voltage. At ambient, optimized for 2.5 V operation. At ambient when 1.25 V reference is selected. Temperature range: 25C to 85C. Temperature range: -40C to +85C.
DVDD = 2.7 V to 5.5 V. V min V max A max pF max
Total for all pins. TA = TMIN to TMAX.
Rev. A | Page 4 of 44
AD5390/AD5391/AD5392
Parameter LOGIC INPUTS (SCL, SDA Only) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)2 Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity2 Midscale/AVDD AIDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5390-51 AD5392-51 0.7 DVDD 0.3 DVDD 1 0.05 DVDD 8 50 AD5391-51 Unit 0.7 DVDD 0.3 DVDD 1 0.05 DVDD 8 50 V min V max A max V min pF typ ns max Test Conditions/Comments SMBus-compatible at DVDD < 3.6 V. SMBus-compatible at DVDD < 3.6 V.
Input filtering suppresses noise spikes of <50 ns. DVDD = 5 V 10%, sinking 200 A. DVDD = 5 V 10%, SDO only, sourcing 200 A. DVDD = 2.7 V to 3.6 V, sinking 200 A. DVDD = 2.7 V to 3.6 V SDO only, sourcing 200 A.
0.4 DVDD - 1 0.4 DVDD - 0.5 1 5
0.4 DVDD - 1 0.4 DVDD - 0.5 1 5
V max V min V max V min A max pF typ
0.4 0.6 1 8 4.5/5.5 2.7/5.5 -85 0.375 0.475 1 1 20 35 20
0.4 0.6 1 8 4.5/5.5 2.7/5.5 -85 0.375 0.475 1 1 20 35 20
V max V max A max pF typ V min/max V min/max dB typ mA/channel max mA/channel max mA max A max A max mW max mW max
ISINK = 3 mA. ISINK = 6 mA.
Outputs unloaded; boost off; 0.25 mA/channel typ. Outputs unloaded; boost on; 0.325 mA/channel typ. VIH = DVDD, VIL = DGND. Typically 200 nA. Typically 3 A. AD5390/AD5391 with outputs unloaded; AVDD = DVDD = 5 V; boost off. AD5392 with outputs unloaded; AVDD = DVDD = 5 V, boost off.
AD539x-5 products are calibrated with a 2.5 V reference. Temperature range for all versions: -40C to +85C. Guaranteed by characterization, not production tested. Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-5 products with a reference of 1.25 V leads to a degradation in performance accuracy. 4 Accuracy guaranteed from VOUT = 10 mV to AVDD - 50 mV.
1 2 3
Rev. A | Page 5 of 44
AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS
AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 3. AD5390-5/AD5391-5/AD5392-5 AC Characteristics1
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 Slew rate2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.1 Hz to 10 Hz) Output Noise Spectral Density @ 1 kHz @ 10 kHz All1 Unit Test Conditions/Comments
8 10 6 8 3 2 12 15 100 1 0.8 0.1 15 40 150 100
s typ s max s typ s max V/s typ V/s typ nV-s typ mV typ dB typ nV-s typ nV-s typ nV-s typ V p-p typ V p-p typ nV/(Hz)1/2 typ nV/(Hz)1/2 typ
1/4 scale to 3/4 scale change settling to 1 LSB. 1/4 scale to 3/4 scale change settling to 1 LSB. Boost mode on. Boost mode off.
See Terminology section. See Terminology section. Effect of input bus activity on DAC output under test. External reference midscale loaded to DAC. Internal reference midscale loaded to DAC.
1 2
Guaranteed by characterization, not production tested. The slew rate can be adjusted via the current boost control bit in the DAC control register.
Rev. A | Page 6 of 44
AD5390/AD5391/AD5392 AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 4.
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Offset Error Offset Error TC Gain Error Gain Temperature Coefficient2 DC Crosstalk REFERENCE INPUT/OUTPUT Reference Input2 Reference Input Voltage DC Input Impedance Input Current Reference Range Reference Output3 AD5390-31 AD5392-31 14 4 -1/+2 4 4 5 0.024 0.1 2 0.5 AD5391-31 Unit 12 1 1 4 4 5 0.024 0.1 2 0.5 Bits LSB max LSB max mV max mV max V/C typ % FSR max % FSR max ppm FSR/C typ mV max Test Conditions/Comments
Guaranteed monotonic over temperature. Measured at code 64 in the linear region. At 25C. TMIN to TMAX.
1.25 1 1 1 V to AVDD/2
1.25 1 1 1 V to AVDD/2
V M min A max V min/max
1% for specified performance. Typically 100 M. Typically 30 nA. Enabled via internal/external bit in control register. REF select bit in control register selects the reference voltage. At ambient. Optimized for 1.25 V operation. At ambient when 2.5 V reference is selected. Temperature range: 25C to 85C. Temperature range: -40C to +85C.
Output Voltage Reference TC Output Impedance OUTPUT CHARACTERISTICS2 Output Voltage Range4 Short-Circuit Current Load Current Capacitive Load Stability RL = RL = 5 k DC Output Impedance MONITOR OUTPUT PIN2 Output Impedance Three-State Leakage Current LOGIC INPUTS2 VIH, Input High Voltage VIL, Input Low Voltage Input Current Pin Capacitance Logic Inputs (SCL, SDA Only) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis
1.245/1.255 2.47/2.53 10 15 2.2 0/AVDD 40 1 200 1,000 0.5 500 100 2 0.8 10 10 0.7 DVDD 0.3 DVDD 1 0.05 DVDD
1.245/1.255 2.47/2.53 10 15 2.2 0/AVDD 40 1 200 1,000 0.5 500 100 2 0.8 10 10 0.7 DVDD 0.3 DVDD 1 0.05 DVDD
V min/max V min/max ppm max ppm max k typ V min/max mA max mA max pF max pF max max typ nA typ
DVDD = 2.7 V to 5.5 V. V min V max A max pF max V min V max A max V min
Total for all pins. TA = TMIN to TMAX.
SMBus-compatible at DVDD < 3.6 V. SMBus-compatible at DVDD < 3.6 V.
Rev. A | Page 7 of 44
AD5390/AD5391/AD5392
Parameter Glitch Rejection Logic Outputs (BUSY, SDO)2 Output Low Voltage Output High Voltage AD5390-31 AD5392-31 50 0.4 DVDD - 0.5 DVDD - 0.1 High Impedance Leakage Current High Impedance Output Capacitance Logic Output (SDA)2 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity2 Midscale/AVDD AIDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation 1 5 AD5391-31 50 0.4 DVDD - 0.5 DVDD - 0.1 1 5 Unit ns max V max V min V min A max pF typ Test Conditions/Comments Input filtering suppresses noise spikes <50 ns. DVDD = 2.7 V to 5.5 V, sinking 200 A. DVDD = 2.7 V to 3.6 V, SDO only, sourcing 200 A. DVDD = 4.5 V to 5.5 V, SDO only, sourcing 200 A.
0.4 0.6 1 8
0.4 0.6 1 8
V max V max A max pF typ
ISINK = 3 mA. ISINK = 6 mA.
2.7/3.6 2.7/5.5 -85 0.375 0.475 1 1 20 21
2.7/3.6 2.7/5.5 -85 0.375 0.475 1 1 20 21
V min/max V min/max dB typ mA/channel max mA/channel max mA max A max A max mW max
Outputs unloaded; boost off; 0.25 mA/channel typ. Outputs unloaded; boost on; 0.325 mA/channel typ. VIH = DVDD, VIL = DGND.
AD5390/AD5391 with outputs unloaded; AVDD = DVDD = 3 V; boost off. AD5392 with outputs unloaded; AVDD = DVDD = 3 V; boost off.
12
12
mW max
1 2
AD539x-3 products are calibrated with a 1.25 V reference. Temperature range for all versions: -40C to +85C. Guaranteed by characterization, not production tested. 3 Programmable either to 1.25 V typ or 2.5 V typ via the AD539x control register. Operating the AD539x-3 products with a reference of 2.5 V leads to a degradation in performance accuracy. 4 Accuracy guaranteed from VOUT = 39 mV to AVDD - 50 mV.
Rev. A | Page 8 of 44
AD5390/AD5391/AD5392 AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS
AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND. Table 5. AD5390-3/AD5391-3/AD5392-3 AC Characteristics1
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 Slew Rate2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough OUTPUT NOISE (0.1 Hz to 10 Hz) Output Noise Spectral Density @ 1 kHz @ 10 kHz All Unit Test Conditions/Comments
8 10 6 8 3 2 12 15 100 1 0.8 0.1 15 40 150 100
s typ s max s typ s max V/s typ V/s typ nV-s typ mV typ dB typ nV-s typ nV-s typ nV-s typ V p-p typ V p-p typ nV/(Hz)1/2 typ nV/(Hz)1/2 typ
1/4 scale to 3/4 scale change settling to 1 LSB. 1/4 scale to 3/4 scale change settling to 1 LSB. Boost mode on. Boost mode off.
See Terminology section. See Terminology section. Effect of input bus activity on DAC output under test. External reference midscale loaded to DAC. Internal reference midscale loaded to DAC.
1 2
Guaranteed by design and characterization, not production tested. The slew rate can be programmed via the current boost control bit in the AD539x control registers.
Rev. A | Page 9 of 44
AD5390/AD5391/AD5392 TIMING CHARACTERISTICS: SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 6. 3-Wire Serial Interface1
Parameter2, 3 t1 t2 t3 t4 t54 t64 t7 t7A t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t17 t18 t19 t205 t214 t224 t234 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.5 30 670 20 20 100 0 100 8 6 20 12 20 5 8 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns max ns min ns min s typ s typ ns min s max ns max ns min ns min ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 24th SCLK falling edge to SYNC falling edge Minimum SYNC low time Minimum SYNC high time Minimum SYNC high time in readback mode Data setup time Data hold time 24th SCLK falling edge to BUSY falling edge BUSY pulse width low (single channel update) 24th SCLK falling edge to LDAC falling edge LDAC pulse width low BUSY rising edge to DAC output response time BUSY rising edge to LDAC falling edge LDAC falling edge to DAC output response time DAC output settling time, AD5390/AD5392 DAC output settling time, AD5391 CLR pulse width low CLR pulse activation time SCLK rising edge to SDO valid SCLK falling edge to SYNC rising edge SYNC rising edge to SCLK rising edge SYNC rising edge to LDAC falling edge
1 2
Guaranteed by design and characterization, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, Figure 4, and Figure 5. 4 Standalone mode only. 5 Daisy-chain mode only.
Rev. A | Page 10 of 44
AD5390/AD5391/AD5392
t1
SCLK 24 48
t7
SYNC
t3 t4 t8 t9
t2 t21
t22
DIN
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N+1
t20
SDO DB23
DB0
UNDEFINED
INPUT WORD FOR DAC N
t23
03773-0-002
03773-0-005
t13
LDAC
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)
t1
SCLK 1 2 24 24
t4
SYNC
t3 t6 t8 t9
t2
t5
t7
DIN
DB23
DB0
t10
BUSY
t11 t12 t13 t17 t14 t15 t13 t17
LDAC1 VOUT1
LDAC2
VOUT2
t16 t18
CLR
t19
VOUT
1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE DURING BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
Rev. A | Page 11 of 44
AD5390/AD5391/AD5392
SCLK 24 48
t7A
SYNC
DIN
DB23
DB0
DB23'
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO DB23
NOP CONDITION DB0
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
200A TO OUTPUT PIN
IOL
VOH (MIN) OR CL 50pF 200A IOH VOL (MAX)
03773-0-003
Figure 5. Load Circuit for Digital Output Timing
Rev. A | Page 12 of 44
03773-0-006
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
AD5390/AD5391/AD5392 TIMING CHARACTERISTICS: I2C SERIAL INTERFACE
Guaranteed by design and characterization, not production tested. DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 7.
Parameter1 FSCL t1 t2 t3 t4 t5 t62 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.1 CB 400 Unit kHz max s min s min s min s min ns min s max s min s min s min s min ns max ns min ns max ns min ns max ns min pF max Description SCL clock frequency SCL cycle time tHIGH, SCL high time tLOW, SCL low time tHD, STA, start/repeated start condition hold time tSU, DAT, data setup time tHD, DAT data hold time tHD, DAT data hold time tSU, STA setup time for repeated start tSU, STO stop condition setup time tBUF, bus free time between a stop and a start condition tF, fall time of SDA when transmitting tR, rise time of SCL and SDA when receiving (CMOS-compatible) tF, fall time of SDA when transmitting tF, fall time of SDA when receiving (CMOS-compatible) tF, fall time of SCL and SDA when receiving tF, fall time of SCL and SDA when transmitting Capacitive load for each bus line
CB3
1 2
See Figure 6. A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of SCL's falling edge. 3 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START CONDITION
t6
t2
t5
t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
03773-0-007
Figure 6. I2C Interface Timing Diagram
Rev. A | Page 13 of 44
AD5390/AD5391/AD5392 ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25C, unless otherwise noted. Table 8.
Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND VREF to AGND REFOUT to AGND AGND to DGND VOUTX to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature (TJ max) 64-Lead LFCSP Package, JA 52-lLad LQFP Package, JA Reflow Soldering Peak Temperature Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to DVDD + 0.3 V -0.3 V to DVDD + 0.3 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +0.3 V -0.3 V to AVDD + 0.3 V -40C to +85C -65C to +150C 150C 22C/W 38C/W 230C
Stresses above absolute maximum ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 14 of 44
AD5390/AD5391/AD5392 PIN CONFIGURATON AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CLR DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1 LDAC
52 51 50 49 48 47 46 45 44 43 42 41 40
NC NC NC NC NC NC REF_GND REFOUT/REFIN SIGNAL_GND 1 DAC_GND 1 AVDD 1 VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD5390/ AD5391
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC BUSY RESET NC NC NC NC NC NC NC NC AVDD 2 AGND 2 VOUT 15 VOUT 14 VOUT 13
CLR NC NC REF_GND REFOUT/REFIN SIGNAL_GND 1 DAC_GND 1 AVDD 1 VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4
DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
39
PIN 1 INDICATOR
38 37 36 35
AD5390/ AD5391
TOP VIEW (Not to Scale)
34 33 32 31 30 29 28 27
LDAC BUSY RESET NC NC NC NC AVDD 2 AGND 2 VOUT 15 VOUT 14 VOUT 13 SIGNAL_GND 2
NC = NO CONNECT
03773-0-008
AGND 1 NC NC VOUT 5 VOUT 6 VOUT 7 MON_IN 1 MON_IN 2 MON_OUT VOUT 8 VOUT 9 VOUT 10 VOUT 11 VOUT 12 DAC_GND 2 SIGNAL_GND 2
AGND 1 VOUT 5 VOUT 6 VOUT 7 MON_IN 1 MON_IN 2 MON_OUT VOUT 8 VOUT 9 VOUT 10 VOUT 11 VOUT 12 DAC_GND 2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 7. AD5390/AD5391 LFCSP Pin Configuration
Figure 9. AD5390/AD5391 LQFP Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CLR DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1 LDAC
52 51 50 49 48 47 46 45 44 43 42 41 40
NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 REF_GND 7 REFOUT/REFIN 8 SIGNAL_GND 1 9 DAC_GND 1 10 AVDD 1 11 VOUT 0 12 VOUT 1 13 VOUT 2 14 VOUT 3 15 VOUT 4 16 NC = NO CONNECT
PIN 1 INDICATOR
AD5392
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC BUSY RESET NC NC NC NC NC NC NC NC NC NC NC NC NC
CLR NC NC REF_GND REFOUT/REFIN SIGNAL_GND 1 DAC_GND 1 AVDD 1 VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4
DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
39
PIN 1 INDICATOR
38 37 36 35
AD5392
TOP VIEW (Not to Scale)
34 33 32 31 30 29 28 27
LDAC BUSY RESET NC NC NC NC NC NC NC NC NC SIGNAL_GND 2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AGND 1 VOUT 5 VOUT 6 VOUT 7 MON_IN 1 MON_IN 2 MON_OUT NC NC
NC
NC
AGND 1 NC NC VOUT 5 VOUT 6 VOUT 7 MON_IN 1 MON_IN 2 MON_OUT NC NC NC NC NC DAC_GND 2 SIGNAL_GND 2
Figure 8. AD5392 LFCSP Pin Configuration
03773-0-009
Figure 10. AD5392 LQFP Pin Configuration
Rev. A | Page 15 of 44
03773-0-011
NC = NO CONNECT
NC DAC_GND 2
03773-0-010
AD5390/AD5391/AD5392
Table 9. Pin Function Descriptions
Mnemonic VOUTX SIGNAL_GND (1, 2) DAC_GND (1, 2) AGND (1, 2) AVDD (1, 2) DGND DVDD REF_GND REFOUT/REFIN Function Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 k to ground. Typical output impedance is 0.5 . Analog Ground Reference Points for each group of eight output channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD539x. Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit DACs. These pins should be connected to the AGND plane. Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane. Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins should be decoupled with 0.1 uF ceramic capacitors and 10 F tantalum capacitors. Operating range is 5 V 10%. Ground for All Digital Circuitry. Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. Recommended that these pins be decoupled with 0.1 F ceramic capacitors and 10 F tantalum capacitors to DGND. Ground Reference Point for the Internal Reference. Connect to AGND. The AD539x contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference output. If the application necessitates the use of an external reference, it can be applied to this pin and the internal reference disabled via the control register. The default for this pin is a reference input. Analog Output Pin. When the monitor function is enabled on the AD5390/AD5391, the MON_OUT acts as the output of a 16-to-1 channel multiplexer, which can be programmed to multiplex any channel output to the MON_OUT pin. When the monitor function is enabled on the AD5392, the MON_OUT acts as the output of an 8-to-1 channel multiplexer that can be programmed to multiplex any channel output to the MON_OUT pin. The MON_OUT pin output impedance is typically 500 and is intended to drive a high input impedance such as that exhibited by SAR ADC inputs. Monitor Input Pins. The AD539x contains two monitor input pins to which the user can connect input signals (within the maximum ratings of the device) for monitoring purposes. Any of the signals applied to the MON_IN pins along with the output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals. Serial Interface Pin.This is the frame synchronization input signal for the serial interface. When taken low, the internal counter is enabled to count the required number of clocks before the addressed register is updated. In I2C mode, AD0 acts as a hardware address pin. Interface Control Pin. Operation is determined by the interface select bit SPI/I2C. Serial Interface Mode: Daisy-Chain Select Input (level-sensitive, active high). When high, this pin enables daisy-chain operation to allow a number of devices to be cascaded together. I2C Mode: This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address for this device on the I2C bus. Serial Data Output. Three-statable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register. During this time, the user can continue writing new data to further the x1, c, and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low this event is stored. BUSY also goes low during power-on reset and when the RESET pin is low. During this time the interface is disabled and any events on LDAC are ignored. A CLR operation also brings BUSY low. Load DAC Logic Input (active low). If LDAC is taken low while BUSY is inactive (high), the contents of the input registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored. Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, all channels are updated with the data contained in the CLR code register. BUSY is low for a duration of 20 s (AD5390/91) and 15 s (AD5392) while all channels are being updated with the CLR code. Asynchronous Digital Reset Input (falling edge sensitive). The function of this pin is equivalent to that of the power-on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence takes 270 s max. This falling edge of RESET initiates the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation and the status of the RESET pin is ignored until the next falling edge is detected.
MON_OUT
MON_IN (1, 2)
SYNC/AD0
DCEN/AD1
SDO BUSY
LDAC
CLR
RESET
Rev. A | Page 16 of 44
AD5390/AD5391/AD5392
Mnemonic PD Function Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 A analog current and 20 A digital current. In power-down mode, all internal analog circuitry is placed in low power mode; the analog output is configured as high impedance outputs or provides a 100 k load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down. Interface Select Input Pin. When this input is low, I2C mode is selected. When this input is high, SPI mode is selected. Interface CLOCK Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock speeds up to 50 MHz. I2C mode: In I2C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I2C mode is compatible with both 100 kHz and 400 kHz operating modes. Interface Data Input Pin. SPI/I2C = 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK. SPI/I2C = 0, I2C mode: In I2C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
SPI/I2C SCLK/SCL
DIN/SDA
Rev. A | Page 17 of 44
AD5390/AD5391/AD5392 TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSBs). Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Zero-Scale Error Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2n-1, VOUT(Zero Scale) = 0 V. Zero-scale error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV. It is mainly caused by offsets in the output amplifier. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD539x-5 with code 32 loaded in the DAC register and with code 64 loaded in the DAC register on the AD539x-3. Gain Error Gain error is specified in the linear region of the output range between VOUT = 10 mV and VOUT = AVDD - 50 mV. It is the deviation in slope of the DAC transfer characteristic from ideal and is expressed in % FSR with the DAC output unloaded. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSBs. DC Output Impedance This is the effective output source resistance. It is dominated by package lead resistance. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change and measured from the rising edge of BUSY. Digital-to-Analog Glitch Energy This is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is defined as the glitch impulse that appears at the output of one DAC due to both the digital change and subsequent analog output change at another DAC. The victim channel is loaded with midscale, and DAC-to-DAC crosstalk is specified in nV-s. Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s. Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs can be capacitively coupled both across and through the device to show up as noise on the VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Output Noise Spectral Density This is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/(Hz)1/2 in a 1 Hz bandwidth at 10 kHz.
Rev. A | Page 18 of 44
AD5390/AD5391/AD5392 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 1.5 1.0
INL ERROR (LSB)
AVDD = DVDD = 5.5V VREF = 2.5V TA = 25C
1.00 0.75 0.50
0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 INPUT CODE 12288 16384
03773-0-040
INL ERROR (LSB)
0.25 0 -0.25 -0.50 -0.75 -1.00
03773-0-043
0
512
1024
1536 2048 2560 INPUT CODE
3072
3584
4096
Figure 11. AD5390-5/AD5392-5 Typical INL Plot
2.0 1.5 1.0
INL ERROR (LSB)
Figure 14. Typical AD5391-5 INL Plot
1.00 0.75 0.50
AVDD = DVDD = 3V VREF = 1.25V TA = 25C
0.5 0 -0.5 -1.0 -1.5 -2.0 0 4096 8192 INPUT CODE 12288 16384
03773-0-041
INL ERROR (LSB)
0.25 0 -0.25 -0.50 -0.75 -1.00
03773-0-044
0
512
1024
1536 2048 2560 INPUT CODE
3072
3584
4096
Figure 12. AD5390-3/AD5392-5 INL Plot
14 12 10 8 6 4 2 0
03773-0-042
Figure 15. Typical AD5391-3 INL Plot
40
AVDD = 5.5V REFIN = 2.5V TA = 25C
AVDD = 5V REFOUT = 2.5V 35 TEMP. RANGE = 25C TO 85C SAMPLE SIZE = 162
30
NUMBER OF UNITS
FREQUENCY
25 20 15 10 5 0 -5.0 -4.0 -3.0 -2.0 -1.0 0 1.0 2.0 3.0 4.0 5.0 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 REFERENCE DRIFT (ppm/C)
-2
-1 0 1 INL ERROR DISTRIBUTION (LSB)
2
Figure 13. AD5390/AD5392 INL Histogram Plot
Figure 16. AD539x REFOUT Temperature Coefficient
Rev. A | Page 19 of 44
03773-0-045
AD5390/AD5391/AD5392
6 WR BUSY 5 3/4 SCALE 4 3 2 1 ZERO SCALE 0
03773-0-046
FULL SCALE AVDD = DVDD = 5V VREF = 2.5V TA = 25C
AVDD = DVDD = 5V VREF = 2.5V TA = 25C EXITS SOFT PD TO MIDSCALE
VOUT (V)
MIDSCALE
1/4 SCALE
VOUT
-1 -40
-20
-10
-5
-2 0 2 CURRENT (mA)
5
10
20
40
Figure 17. AD539x Exiting Soft Power-Down
0.20
Figure 20. AD539x-5 Source and Sink Capability
PD
0.15 0.10
AVDD = 5V VREF = 2.5V TA = 25C
ERROR VOLTAGE (V)
ERROR AT ZERO SINKING CURRENT 0.05 0 -0.05 -0.10 -0.15 (VDD-VOUT) AT FULL-SCALE SOURCING CURRENT
VOUT
AVDD = DVDD = 5V VREF = 2.5V TA = 25C EXITS HARDWARE PD TO MIDSCALE
03773-0-047
-0.20 0 0.25 0.50 0.75 1.00 1.25 ISOURCE/ISINK (mA) 1.50 1.75 2.00
Figure 18. AD539x Exiting Hardware Power-Down
2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 0
Figure 21. Headroom at Rails vs. Source/Sink Current
AVDD = DVDD = 5V VREF = 2.5V TA = 25C 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 10nV-s
AVDD = DVDD = 5V VREF = 2.5V TA = 25C POWER SUPPLY RAMP RATE = 10ms VOUT
AMPLITUDE (V)
AVDD
03773-0-048
50
100
150
200 250 300 350 SAMPLE NUMBER
400
450
500
550
Figure 19. AD539x Power-Up Transient
Figure 22. AD539x-5 Glitch Impulse Energy
Rev. A | Page 20 of 44
03773-0-051
03773-0-050
03773-0049
AD5390/AD5391/AD5392
1.254 1.253 1.252 1.251
AMPLITUDE (V)
1.250 1.249 1.248 1.247 1.246 1.245 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550
03773-0-052
NUMBER OF UNITS
AVDD = DVDD = 3V VREF = 1.25V TA = 25C 14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s
10
DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25C
8
6
4
0
0.4
0.5
0.6 0.7 DIDD (mA)
0.8
0.9
Figure 23. AD539x-3 Glitch Impulse
Figure 26. AD539x DIDD Histogram
2.456
AVDD = DVDD = 5V VREF = 2.5V TA = 25C
AMPLITUDE (V)
2.455 2.454 2.453 2.452 2.451
03773-0-053
AVDD = DVDD = 5V VREF = 2.5V TA = 25C 14ns/SAMPLE NUMBER
VOUT
2.450 2.449 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 500 550
03773-0-056
03773-0-057
Figure 24. AD539x Slew Rate Boost Off
600
Figure 27. AD539x Adjacent Channel Crosstalk
500
OUTPUT NOISE (nV/ Hz)
AVDD = 5V TA = 25C REFOUT DECOUPLED WITH 100nF CAPACITOR
400
AVDD = DVDD = 5V VREF = 2.5V TA = 25C
VOUT
300
REFOUT = 2.5V
200
REFOUT = 1.25V
03773-0-054
100
0 100
1k FREQUENCY (Hz)
10k
100k
Figure 25. AD539x Slew Rate Boost On
Figure 28. AD539x REFOUT Noise Spectral Density
Rev. A | Page 21 of 44
03773-0-055
2
AD5390/AD5391/AD5392
AVDD = DVDD = 5V TA = 25C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5V/DIV X AXIS = 100ms/DIV 6 5 4 3/4 SCALE
VOUT (V)
AVDD = DVDD = 3V VREF = 1.25V TA = 25C
3 2 1
MIDSCALE
FULL SCALE
03773-0-058
0 -1 -40
03773-0-059
ZERO SCALE -20 -10 -5
1/4 SCALE -2 0 2 CURRENT (mA) 5 10 20 40
Figure 29. 0.1 Hz to 10 Hz Output Noise Plot
Figure 30. AD539x-3 Source and Sink Current Capability
Rev. A | Page 22 of 44
AD5390/AD5391/AD5392 FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE--GENERAL
The AD5390/AD5391 are complete single-supply, 16-channel, voltage output DACs offering a resolution of 14 bits and 12 bits, respectively. The AD5392 is a complete single-supply, 8-channel, voltage output DAC offering 14-bit resolution. All devices are available in 64-lead LFCSP and 52-lead LQFP packages and feature serial interfaces. This family includes an internal selectable 1.25 V/2.5 V, 10 ppm/C reference that can be used to drive the buffered reference inputs (alternatively, an external reference can be used to drive these inputs). All channels have an onchip output amplifier with rail-to-rail output capable of driving a 5 k in parallel with a 200 pF load. The architecture of a single DAC channel consists of a 12-bit and 14-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guarantees DAC monotonicity. The 12-bit and 14-bit binary digital code loaded to the DAC register deter-mines at what node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers, allowing the user to digitally trim offset and gain.
VREF x1 INPUT REG INPUT DATA m REG c REG x2 DAC REG 14-BIT DAC R R VOUT AVDD
The digital input transfer function for each DAC can be represented as
x 2 = ( (m + 2) / 2n ) x x1 + c - 2n -1
where:
(
)
x2 is the data-word loaded to the resistor-string DAC. x1 is the 12-bit and 14-bit data-word written to the DAC input register. m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB of the gain coefficient is zero. n = DAC resolution (n = 14 for the AD5390/AD5392 and n = 12 for the AD5391). c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on the AD5390/AD5392 and 0x800 on the AD5391). The complete transfer function for these devices can be represented as VOUT = 2 x VREF x x 2 / 2n where: x2 is the data-word loaded to the resistor-string DAC. VREF is the reference voltage applied to the REFIN/REFOUT pin on the DAC when an external reference is used, 2.5 V for specified performance on the AD539x-5 products and 1.25 V on the AD539x-3 products.
Figure 31. AD5390/92 Single-Channel Architecture
These registers let the user calibrate out errors in the complete signal chain including the DAC using the internal m and c registers, which hold the correction factors. All channels are double-buffered, allowing synchronous updating of all channels using the LDAC pin. Figure 31 shows a block diagram of a single channel on the AD5390/AD5391/AD5392.
03773-0-018
Rev. A | Page 23 of 44
AD5390/AD5391/AD5392
DATA DECODING--AD5390/AD5392
The AD5390/AD5392 contain an internal 14-bit data bus. The input data is decoded depending on the data loaded to the REG1 and REG0 bits of the input serial register. This is shown in Table 10. Data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data, and the offset (c) and gain (m) register contents are shown in Table 11 to Table 13. Table 10. Register Selection
REG1 1 1 0 0 REG0 1 0 1 0 Register Selected Input data register (x1) Offset register (c) Gain register (m) Special function registers (SFRs)
DATA DECODING--AD5391
The AD5391contains an internal 12-bit data bus. The input data is decoded depending on the value loaded to the REG1 and REG0 bits of the input serial register. The input data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data and the offset (c) and gain (m) register contents are shown in Table 14 to Table 16. Table 14. AD5391 DAC Data Format (REG1 = 1, REG0 = 1)
DB11 to DB0 1111 1111 1111 1111 1000 0000 1000 0000 0111 1111 0000 0000 0000 0000 1111 1110 0001 0000 1111 0001 0000 DAC Output (V) 2 VREF x (4095/4096) 2 VREF x (4094/4096) 2 VREF x (2049/4096) 2 VREF x (2048/4096) 2 VREF x (2047/4096) 2 VREF x (1/4096) 0
Table 11. AD5390/AD5392 DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0 11 1111 1111 11 1111 1111 10 0000 0000 10 0000 0000 01 1111 1111 00 0000 0000 00 0000 0000 1111 1110 0001 0000 1111 0001 0000 DAC Output (V) 2 VREF x (16383/16384) 2 VREF x (16382/16384) 2 VREF x (8193/16384) 2 VREF x (8192/16384) 2 VREF x (8191/16384) 2 VREF x (1/16384)V 0
Table 15. AD5391 Offset Data Format (REG1 = 1, REG0 = 0)
DB11 to DB0 1111 1111 1111 1111 1000 0000 1000 0000 0111 1111 0000 0000 0000 0000 1111 1110 0001 0000 1111 0001 0000 Offset (LSB) +2048 +2047 +1 +0 -1 -2047 -2048
Table 12. AD5390/AD5392 Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0 111111 1111 111111 1111 100000 0000 100000 0000 011111 1111 000000 0000 000000 0000 1111 1110 0001 0000 1111 0001 0000 Offset (LSB) +8192 +8191 +1 +0 -1 -8191 -8192
Table 16. AD5391 Gain Data Format (REG1 = 0, REG0 = 1)
DB11 to DB0 1111 1111 1011 1111 0111 1111 0011 1111 0000 0000 1110 1110 1110 1110 0000 Gain Factor 1 0.75 0.5 0.25 0
Table 13. AD5390/AD5392 Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0 11 1111 1111 10 1111 1111 01 1111 1111 00 1111 1111 00 0000 0000 1110 1110 1110 1110 0000 Gain Factor 1 0.75 0.5 0.25 0
Rev. A | Page 24 of 44
AD5390/AD5391/AD5392 INTERFACES
The AD5390/AD5391/AD5392 contain a serial interface that can be programmed to be either DSP-, SPI-, and MICROWIREcompatible, or I2C-compatible. The SPI/I2C pin is used to select the interface mode. To minimize both the power consumption of the device and the on-chip digital noise, the interface powers up fully only when the device is being written to--that is, on the falling edge of SYNC. Logic 1 pin to configure this mode of operation. The serial interface control pins are described in Table 17. Table 17. Serial Interface Control Pins
Pin SYNC, DIN, SCLK DCEN SDO Description Standard 3-wire interface pins. Selects standalone mode or daisy-chain mode. Data out pin for daisy-chain mode.
DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL INTERFACE
The serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. Daisy-chaining allows many devices to be cascaded together to increase system channel count. The SPI/I2C pin is tied to a
Figure 2 to Figure 4 show timing diagrams for a serial write to the AD5390/AD5391/AD5392 in both standalone and daisychain mode. The 24-bit data-word format for the serial interface is shown in Table 18 to Table 20. Descriptions of the bits follow in Table 21.
Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration
MSB A/B R/W 0 0 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0
Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration
MSB A/B R/W 0 0 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X LSB X
Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration
MSB A/B R/W 0 0 0 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 LSB DB0
Table 21. Serial Input Register Configuration Bit Descriptions
Bit A/B R/W A3 to A0 REG1 and REG0 DB13 to DB0 X Description When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode disabled, this bit should be set to zero to select the A data register. The read or write control bit. Used to address the input channels. Select the register to which data is written, as outlined in Table 10. Contain the input data-word. Don't care condition.
Rev. A | Page 25 of 44
AD5390/AD5391/AD5392
Standalone Mode
By connecting the daisy-chain enable (DCEN) pin low, standalone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits is shifted into the serial shift register. Any further edges on SYNC except for a falling edge are ignored until 24 bits are clocked in. Once 24 bits have been shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. If SYNC is taken high before 24 clocks are clocked into the part, it is considered a bad frame and the data is discarded. The serial clock can be either a continuous or a gated clock. A continuous SCLK source can be used only if the SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC taken high after the final clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the serial input register write sequence. With R/W = 1, Bits A3 to A0 in association with Bits REG1 and REG0 select the register to be read. The remaining data bits in the write sequence are don't care bits. During the next SPI write, the data appearing on the SDO output contains the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. The readback diagram in Figure 32 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD539x, the following sequence should be implemented. First, write 0x404XXX to the AD539x input register. This configures the AD539x for read mode with the m register of Channel 0 selected. Note that all Data Bits DB13 to DB0 are don't care bits. Follow this with a second write, a NOP condition, and 0x000000. During this write, the data from the m register is clocked out on the DOUT line--that is, data clocked out contains the data from the m register in Bits DB13 to DB0, and the top 10 bits contain the address information as previously written. In readback mode, the SYNC signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback, then the first bit of data is clocked out on the falling edge of SYNC.
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be used to daisy-chain the devices together. This daisy-chain mode can be useful in system diagnostics and for reducing the number of serial interface lines. By connecting the DCEN pin high, daisy-chain mode is enabled. The first falling edge of SYNC starts the write cycle. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. For each device in the system, 24 clock pulses are required. Therefore, the total number of clock cycles must equal 24N where N is the total number of AD539x devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register.
SCLK 24 48
SYNC
DIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES REGISTER TO BE READ
NOP CONDITION
SDO
DB23
DB0
DB23
DB0
03773-0-022
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
Figure 32. AD539x Readback Operation
Rev. A | Page 26 of 44
AD5390/AD5391/AD5392 I2C SERIAL INTERFACE
The AD5390/AD5391/AD5392 products feature an I2Ccompatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the DACs and the master at rates up to 400 kHz. Figure 4 shows the 2-wire interface timing diagram. When selecting the I2C operating mode by configuring the SPI/I2C pin to Logic 0, the device is connected to the I2C bus as a slave device (that is, no clock is generated by the device). The AD5390/AD5391/AD5392 have a 7-bit slave address 1010 1(AD1)(AD0). The five MSBs are hard-coded and the two LSBs are determined by the state of the AD1 and AD0 pins. The hardware configuration facility for the AD1 and AD0 pins allows four of these devices to be configured on the bus.
REPEATED START CONDITION
A repeated START (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus.
ACKNOWLEDGE BIT (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. An ACK is always generated by the receiving device. The AD539x devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring the ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication.
I C DATA TRANSFER
One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP Conditions. Both SDA and SCL are pulled high by the external pull-up resistors when the I2C bus is not busy.
2
AD539x SLAVE ADDRESSES
A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address. When idle, the AD539x device waits for a START condition followed by its slave address. The LSB of the address word is the read/write (R/W) bit. The AD539x devices are receive devices only, and R/W = 0 when communicating with them. After receiving the proper address 1010 1(AD1) (AD0), the AD539x issues an ACK by pulling SDA low for one clock cycle. The AD539x has four user-programmable addresses determined by the AD1 and AD0 bits.
START AND STOP CONDITIONS
A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition from the master signals the beginning of a transmission to the AD539x. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active.
Rev. A | Page 27 of 44
AD5390/AD5391/AD5392 I2C WRITE OPERATION
There are three specific modes in which data can be written to the AD539x family of DACs. in the DAC to be addressed and is also acknowledged by the DAC. Address Bits A3 to A0 address all channels on the AD5390/AD5391. Address Bits A2 to A0 address all channels on the AD5392. Address Bit A3 is a zero on the AD5392. Two bytes of data then are written to the DAC, as shown in Figure 33. A STOP condition follows. This lets the user update a single channel within the AD539x at any time and requires four bytes of data to be transferred from the master.
4-BYTE MODE
When writing to the AD539x DACs, begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel
SCL
SDA
1 START CONDITION BY MASTER
0
1
0
1
AD1
AD0
R/W
0
0
0
0
A3
A2
A1
A0 ACK BY CONVERTER
ADDRESS BYTE
MSB ACK BY CONVERTER
POINTER BYTE
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB LEAST SIGNIFICANT DATA BYTE
LSB STOP ACK CONDITION BY BY CONVERTER MASTER
Figure 33. The 4-Byte Mode I2C Write Operation
Rev. A | Page 28 of 44
03773-0-023
ACK BY CONVERTER
AD5390/AD5391/AD5392
3-BYTE MODE
The 3-byte mode lets the user update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once and subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the user begins with an address byte (R/W = 0) after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Address Bits A3 to A0 address all channels on the AD5390/AD5391. Address Bits A2 to A0 address all channels on the AD5392. Address Bit A3 is a zero on the AD5392. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated. If a STOP condition is not sent following the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. This mode requires only three bytes to be sent to update any channel once the device has been addressed initially and reduces the software overhead in updating the AD539x channels. A STOP condition at any time exits this mode. Figure 34 shows a typical configuration.
SCL
SDA
1 START CONDITION BY MASTER
0
1
0
1
AD1
AD0
R/W
0
0
0
0
A3
A2
A1
A0 ACK BY CONVERTER
ADDRESS BYTE
ACK MSB BY CONVERTER
POINTER BYTE FOR CHANNEL N
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY CONVERTER
ACK BY CONVERTER DATA FOR CHANNEL N
SCL
SDA
0 MSB
0
0
0
A3
A2
A1
A0 ACK BY CONVERTER
POINTER BYTE FOR CHANNEL NEXT CHANNEL
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB ACK BY CONVERTER LEAST SIGNIFICANT DATA BYTE
LSB ACK STOP BY CONDITION CONVERTER BY MASTER
03773-0-024
DATA FOR CHANNEL NEXT CHANNEL
Figure 34. The 3-Byte Mode I2C Write Operation
Rev. A | Page 29 of 44
AD5390/AD5391/AD5392
2-BYTE MODE
The 2-byte mode lets the user update channels sequentially following initialization of this mode. The device address byte is required only once and the address pointer is configured for autoincrement or burst mode. The user must begin with an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF), which initiates the burst mode of operation. The address pointer initializes to Channel 0 and the data following the pointer is loaded to Channel 0. The address pointer automatically increments to the next address.
SCL
The REG0 and REG1 bits in the data byte determine the register to be updated. In this mode, following the initialization, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0 to the final address and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A STOP condition at any time exits this mode. Toggle mode of operation is not supported in 2-byte mode. Figure 35 shows a typical configuration.
.
SDA START CONDITION BY MASTER SCL
1
0
1
0
1
AD1
AD0
R/W
A7=1
A6=1
A5=1
A4=1
A3=1
A2=1
A1=1
A0=1 ACK BY CONVERTER
ADDRESS BYTE
ACK MSB BY CONVERTER
POINTER BYTE
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY CONVERTER
ACK BY CONVERTER CHANNEL 0 DATA
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY CONVERTER
ACK BY CONVERTER CHANNEL 1 DATA
SCL
SDA
REG1
REG0
MSB MOST SIGNIFICANT DATA BYTE
LSB
MSB LEAST SIGNIFICANT DATA BYTE
LSB ACK BY CONVERTER STOP CONDITION BY MASTER
03773-0-025
ACK BY CONVERTER
CHANNEL N DATA FOLLOWED BY STOP
Figure 35. 2-Byte Mode I2C Write Operation
Rev. A | Page 30 of 44
AD5390/AD5391/AD5392
AD539x ON-CHIP SPECIAL FUNCTION REGISTERS
The AD539x family of parts contains a number of special function registers (SFRs) as shown in Table 22. SFRs are addressed with REG1 = 0 and REG0 = 0 and are decoded using Address Bits A3-A0. Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)
R/ W X 0 0 0 0 0 1 0 0 A3 0 0 0 1 1 1 1 1 1 A2 0 0 0 0 0 1 1 0 1 A1 0 0 1 0 0 0 0 1 1 A0 0 1 0 0 1 0 0 0 1 Function NOP (no operation) Write CLR code Soft CLR Soft power-down Soft power-up Control register write Control register read Monitor channel Soft reset
Soft Power-Down REG1 = REG0 = 0, A3-A0 =1000 DB13-DB0 = Don't Care. Executing this instruction performs a global power-down, which puts all channels into a low power mode, reducing analog current to 1 A maximum and digital power consumption to 20 A maximum. In power-down mode, the output amplifier can be configured as a high impedance output or can provide a 100 k load to ground. The contents of all internal registers are retained in power-down mode. Soft Power-Up REG1 = REG0 = 0, A3-A0 =1001 DB13-DB0 = Don't Care. This instruction is used to power up the output amplifiers and the internal references. The time to exit power-down mode is 8 s. The hardware power-down and software functions are internally combined in a digital OR function. Soft Reset REG1 = REG0 = 0, A5-A0 = 001111 DB13-DB0 = Don't Care. This instruction is used to implement a software reset. All internal registers are reset to their default values, which correspond to m at full scale and c at zero scale. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 s maximum. Monitor Channel REG1 = REG0 = 0, A3-A0 = 01010 DB13-DB8 = Contain data to address the channel to be monitored. A monitor function is provided on all devices. This feature, consisting of a multiplexer addressed via the interface, allows any channel output to be routed to the MON_OUT pin for monitoring using an external ADC. In addition to monitoring all output channels, two external inputs are also provided, allowing the user to monitor signals external to the AD539x. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain the channel address for the monitored channel. On the AD5391 12-bit part, DB11 to DB6 contain the channel address for the channel to be monitored. Selecting Address 63 three-states the MON_OUT pin. The channel monitor decoding for the AD5390/AD5392 is shown in Table 23 and the monitor decoding for the AD5391 is shown in Table 24.
SFR Commands NOP (No Operation) REG1 = REG0 = 0, A3-A0 = 0000 Performs no operation, but is useful in readback mode to clock out data on SDO for diagnostic purposes. BUSY outputs a low during a NOP operation. Write CLR Code REG1 = REG0 = 0, A3-A0 = 0001 DB13-DB0 = Contain the CLR data. Bringing the CLR line low or exercising the soft clear function loads the contents of the DAC registers with the data contained in the user-configurable CLR register and sets VOUT0 to VOUT15, accordingly. This can be very useful not only for setting up a specific output voltage in a clear condition but for calibration purposes. For calibration, the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to all DACs. Default on power-up is all zeros. Soft CLR REG1 = REG0 = 0, A3-A0 = 0010 DB13-DB0 = Don't Care. Executing this instruction performs the CLR, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the CLR code register. The time taken to execute fully the SOFT CLR is 20 s on the AD5390/AD5391 and 15 s on the AD5392, and is indicated by the BUSY low time.
Rev. A | Page 31 of 44
AD5390/AD5391/AD5392
Table 23. AD5390/AD5392 Channel Monitor Decoding
REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 DB12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 DB11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 DB10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 DB9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 DB8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 DB7 to DB0 X X X X X X X X X X X X X X X X X X X MON_OUT (AD5390) VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 VOUT 7 VOUT 8 VOUT 9 VOUT 10 VOUT 11 VOUT 12 VOUT 13 VOUT 14 VOUT 15 MON_IN1 MON_IN2 Three-state MON_OUT (AD5392) VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 VOUT 7
MON_IN1 MON_IN2 Three-state
Table 24. AD5391 Channel Monitor Decoding
REG1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DB11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 DB10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 DB9 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 . 1 1 DB8 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 . 1 1 DB7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . 1 1 DB6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 . 0 1 DB5 to DB0 X X X X X X X X X X X X X X X X X X X X X X MON_OUT (AD5391) VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 VOUT 7 VOUT 8 VOUT 9 VOUT 10 VOUT 11 VOUT 12 VOUT 13 VOUT 14 VOUT 15 MON_IN1 MON_IN2 Undefined Undefined Undefined Three-state
Rev. A | Page 32 of 44
AD5390/AD5391/AD5392
CONTROL REGISTER WRITE
Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0, A3-A0 = 1100, and DB13-DB0 contain the control register data. Table 25. AD5390/AD5392 Control Register Contents
MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0
Table 26. AD5390 and AD5392 Bit Descriptions
Bit CR13 Description Power-Down Status. This bit is used to configure the output amplifier state in power-down mode. CR13 = 1: Amplifier output is high impedance (default on power-up). CR13 = 0: Amplifier output is 100 k to ground. REF Select. This bit selects the operating internal reference for the AD539x. CR12 is programmed as follows: CR12 = 1: Internal reference is 2.5 V (AD5390/AD5392-5 default). Recommended operating reference for AD539x-5. CR12 = 0: Internal reference is 1.25 V (AD5390/AD5392-3 default). Recommended operating reference for AD5390-3 and AD5392-3. Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate and is configured as follows: CR11 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR11 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. Internal/External Reference. This bit determines if the DAC uses its internal reference or an external reference. CR10 = 1: Internal reference enabled. Reference output depends on data loaded to CR12. CR10 = 0: External reference selected (default on power-up). Channel Monitor Enable (see Table 23). CR9 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR9 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated. Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5390/AD5392, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130C. This function can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers, if the die temperature has dropped below 130C. CR8 = 1: Thermal monitor enabled. CR8 = 0: Thermal monitor disabled (default on power-up). Don't Care. Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in toggle mode on the AD5390 and AD5392, as follows: CR3 Group 1 Channels 8 to 15 CR2 Group 0 Channels 0 to 7 CR2 is the only active bit on the AD5392. Logic 1 written to any bit enables a group of channels, and Logic 0 disables a group. LDAC is used to toggle between the two registers. Don't care.
CR12
CR11
CR10
CR9
CR8
CR7 to CR4 CR3 to CR2
CR1 and CR0
Rev. A | Page 33 of 44
AD5390/AD5391/AD5392
Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0, A3-A0 = 1100, and DB13-DB0 contain the control register data.
Table 27. AD5391 Control Register Contents
MSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0
Table 28. AD5391 Bit Descriptions
Bit CR11 Description Power-Down Status. This bit is used to configure the output amplifier state in power-down mode. CR11 = 1: Amplifier output is high impedance (default on power-up). CR11 = 0: Amplifier output is 100 k to ground. REF Select. This bit selects the operating internal reference for the AD5391. CR10 is programmed as follows: CR10 = 1: Internal reference is 2.5 V (AD5391-5 default). Recommended operating reference for AD5391-5. CR10 = 0: Internal reference is 1.25 V (AD5391-3 default). Recommended operating reference for AD5391-3. Current Boost Control. This bit is used to boost the current in the output amplifier, thus altering its slew rate. This bit is configured as follows: CR9 = 1: Boost mode on. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. CR9 = 0: Boost mode off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption. Internal/External Reference. This bits determines if the DAC uses its internal reference or an external reference. CR8 = 1: Internal reference enabled. Reference output depends on data loaded to CR10. CR8 = 0: External reference selected (default on power-up). Channel Monitor Enable (see Table 24). CR7 = 1: Monitor enabled. This enables the channel monitor function. Following a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin. CR7 = 0: Monitor disabled (default on power-up). When monitor is disabled, the MON_OUT pin is three-stated. Thermal Monitor Function. This function is used to monitor the internal die temperature of the AD5391, when enabled. The thermal monitor powers down the output amplifiers when the temperature exceeds 130C. This function can be used to protect the device in cases where the power dissipation of the device may be exceeded, if a number of output channels are simultaneously short circuited. A soft power-up re-enables the output amplifiers if the die temperature has dropped below 130C. CR6 = 1: Thermal monitor enabled. CR6 = 0: Thermal monitor disabled (default on power-up). Don't care. Toggle Function Enable. This function lets the user toggle the output between two codes loaded to the A and B register for each DAC. Control Register Bits CR3 and CR2 are used to enable individual groups of eight channels for operation in toggle mode on the AD5391, as follows: CR1 Group 1 Channels 8-15 CR0 Group 0 Channels 0 to 7 Logic 1 written to any bit enables a group of channels, and Logic 0 disables a group. LDAC is used to toggle between the two registers.
CR10
CR9
CR8
CR7
CR6
CR5 to CR2 CR1 to CR0
Rev. A | Page 34 of 44
AD5390/AD5391/AD5392 HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edgesensitive input. The default corresponds to m at full scale and c at zero scale. The contents of all DAC registers are cleared setting the outputs to 0 V. This sequence takes 270 s maximum. The falling edge of RESET initiates the reset process. BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal operation, and the status of the RESET pin is ignored until the next falling edge is detected.
POWER-ON RESET
The AD539x products contain a power-on reset generator and state machine. The power-on reset resets all registers to a predefined state, and the analog outputs are configured as high impedance outputs. The BUSY pin goes low during the poweron reset sequence, preventing data writes to the device.
POWER-DOWN
The AD539x products contain a global power-down feature that puts all channels into a low power mode, reducing the analog power consumption to 1 A maximum and the digital power consumption to 20 A maximum. In power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 k load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier elapses before the outputs settle to their correct value.
ASYNCHRONOUS CLEAR FUNCTION
CLR is negative-edge-triggered and BUSY goes low for the duration of the CLR execution. Bringing the CLR line low clears the contents of the DAC registers to the data contained in the user-configurable CLR register and sets the analog outputs accordingly. This function can be used in system calibration to load zero scale and full scale to all channels together. The execution time for a CLR is 20 s on the AD5390/AD5391 and 15 s on the AD5392.
MICROPROCESSOR INTERFACING
AD539x to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)--see the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD539x, the MOSI output drives the serial data line (DIN) of the AD539x, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD539x, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the MC8HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.
DVDD
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output indicating the status of the AD539x devices. BUSY goes low during internal calculations of x2 data. If LDAC is taken low while BUSY is low, this event is stored. The user can hold the LDAC input permanently low and, in this case, the DAC outputs update immediately after BUSY goes high. BUSY also goes low during a power-on reset and when a falling edge is detected on the RESET pin. During this time, all interfaces are disabled and any events on LDAC are ignored. The AD539x products contain an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the x2 registers. However, these devices update the DAC register only if the x2 data has changed, thereby removing unnecessary digital crosstalk.
AD539x
SER/PAR
MC68HC11
RESET SDO DIN SCLK SYNC SPI/12C
03773-0-026
MISO MOSI SCK PC7
Figure 36. AD539x-MC68HC11 Interface
Rev. A | Page 35 of 44
AD5390/AD5391/AD5392
AD539x to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In Figure 27, I/O port RA1 is used to pulse SYNC and enable the serial port of the AD539x. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations are needed, depending on the mode. Figure 37 shows the connection diagram.
DVDD
DVDD
AD539x
SER/PAR RESET SPI/12C
8xC51
DVDD
RxD
SDO DIN
03773-0-028
03773-0-029
TxD P1.1
SCLK SYNC
AD539x
SER/PAR RESET SPI/12C
Figure 38. AD539x to 8051 Interface
PIC16C6x/7x
AD539x to ADSP2101/ADSP2103
Figure 39 shows a serial interface between the AD539x and the ADSP2101/ADSP2103. The ADSP2101/ADSP2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP2101/ADSP2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.
SDI/RC4 SDO/RC5 SCK/RC3 RA1
SDO DIN SCLK SYNC
03773-0-027
Figure 37. AD539x to PIC16C6X/7X Interface
DVDD
AD539x
RESET SPI/I2C
AD539x to 8051
The AD539x requires a clock synchronized to the serial data. The 8051 serial interface must, therefore, be operated in mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 38 shows how the 8051 is connected to the AD539x. Because the AD539x shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD539x requires its data with the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account.
ADSP2101/ ADSP2103
DR DT SCK TFS RFS
SDO DIN SCLK SYNC
Figure 39. AD539x to ADSP2101/ADSP2103 Interface
Rev. A | Page 36 of 44
AD5390/AD5391/AD5392 APPLICATION INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD539x is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD539x is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (AVDD, AVCC), it is recommended to tie those pins together. The AD539x should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible--ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD539x should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board, because there is a separate ground plane, but separating the lines helps). Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the soldered side. reference. The reference should be decoupled at the REFOUT/REFIN pin of the device with a 0.1 F capacitor.
AVDD 0.1F DVDD
10F
0.1F
AVDD REFOUT/REFIN 0.1F REF_GND
DVDD VOUT 0
AD539x
VOUT 31 DAC_GND SIGNAL_GND AGND DGND
03773-0-060
Figure 40. Typical Configuration with External Reference
Figure 41 shows a typical configuration when using the internal reference. On power-up, the AD539x defaults to an external reference; therefore, the internal reference needs to be configured and turned on via a write to the AD539x control register. On the AD5390/AD5392 Control Register Bit CR12 lets the user choose the reference voltage; Bit CR10 is used to select the internal reference. It is recommended to use the 2.5 V reference when AVDD = 5 V, and the 1.25 V reference when AVDD = 3 V. On the AD5391, Control Register Bit CR10 lets the user choose the reference voltage; Bit CR8 is used to select the internal reference.
AVDD 0.1F DVDD
ADR431/ ADR421
AVDD
10F
0.1F
DVDD VOUT 0
REFOUT/REFIN 0.1F REF_GND
AD539x
VOUT 31 DAC_GND SIGNAL_GND AGND DGND
03773-0-061
TYPICAL CONFIGURATION CIRCUIT
Figure 40 shows a typical configuration for the AD539x-5 when configured for use with an external reference. In the circuit shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied together to a common AGND. AGND and DGND are connected together at the AD539x device. On power-up, the AD539x defaults to external reference operation. All AVDD lines are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 F ceramic and a 10 F tantalum capacitor. In this application, the reference for the AD539x-5 is provided externally from either an ADR421 or ADR431 2.5 V reference. Suitable external references for the AD539x-3 include the ADR280 1.2 V
Rev. A | Page 37 of 44
Figure 41. Typical Configuration with Internal Reference
AD5390/AD5391/AD5392
Digital connections have been omitted for clarity. The AD539x contains an internal power-on reset circuit with a 10 ms brownout time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD539x as part of the initialization process to ensure the calibration data is loaded correctly into the device. To configure the AD539x for toggle mode of operation, the sequence of events is as follows: 1. 2. 3. 4. Enable toggle mode for the required channels via the control register. Load data to A registers. Load data to B registers. Apply LDAC.
AD539x MONITOR FUNCTION
The AD5390 contains a channel monitor function consisting of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. Table 23 and Table 24 contain the decoding information required to route any channel on the AD5390, AD5391, and AD5392 to the MON_OUT pin. Selecting Channel Address 63 three-states the MON_OUT pin. The AD539x family also contains two monitor input pins called MON_IN1 and MON_IN2. The user can connect external signals to these pins, which under software control can be multiplexed to MON_OUT for monitoring purposes. Figure 42 shows a typical monitoring circuit implemented using a 12-bit SAR ADC in a 6-lead SOT package. The external reference input is connected to MON_IN1 to allow it to be easily monitored. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.
The LDAC is used to switch between the A and B registers in determining the analog output. The first LDAC configures the output to reflect the data in the A registers. This mode offers significant advantages, if the user wants to generate a square wave at the output on all channels as might be required to drive a liquid-crystal-based, variable optical attenuator. Configuring the AD5390, for example, the user writes to the control register and sets CR3 = 1 and CR2 = 1, enabling the two groups of eight for toggle mode operation. The user must then load data to all 16 A registers and B registers. Toggling the LDAC sets the output values to reflect the data in the A and B registers, and the frequency of the LDAC determines the frequency of the square wave output. The first LDAC loads the contents of the A registers to the DAC registers. Toggle mode is disabled via the control register; the first LDAC following the disabling of the toggle mode updates the outputs with the data contained in the A registers.
THERMAL MONITOR FUNCTION
The AD539x family has a temperature shutdown function to protect the chip in case multiple outputs are shorted. The shortcircuit current of each output amplifier is typically 40 mA. Operating the AD539x at 5 V leads to a power dissipation of 200 mW/shorted amplifier. With five channels shorted, this leads to an extra watt of power dissipation. For the 52-lead LQFP, the JA is typically 44C/W. The thermal monitor is enabled by the user using CR8 in the AD5390/AD5392 control register and by CR6 in the AD5391 control register. The output amplifiers on the AD539x are automatically powered down if the die temperature exceeds approximately 130C. After a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130C or by turning off the thermal monitor function via the control register.
DATA REGISTER A
AVDD
AD780/ ADR431
REFOUT/REFIN
DIN SYNC SCLK AVDD
OUTPUT PORT
AD5390
MON_IN1 MON_OUT VOUT 0
AD7476
VIN GND AGND
CS SCLK SDATA
INPUT PORT
CONTROLLER
VOUT 15
DAC_GND SIGNAL GND
03773-0-030
Figure 42. Typical Channel Monitoring Circuit
TOGGLE MODE FUNCTION
The toggle mode function allows an output signal to be generated using the LDAC control signal that switches between two DAC data registers. This function is configured using the SFR control register, as follows. A write with REG1 = REG0 = 0, A3-A0 = 1100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bits CR3 and CR2 in the AD5390/AD5392 control register and using Bits CR1 and CR0 in the AD5391 control register. (See the Control Register Write section.) Figure 43 shows a block diagram of the toggle mode implementation. Each DAC channel on the AD539x contains an A and a B data register. Note that the B registers can be loaded only when toggle mode is enabled.
DAC REGISTER
14-BIT DAC
VOUT
INPUT DATA
INPUT REGISTER
DATA REGISTER B
03773-0-031
A/B
LDAC CONTROL INPUT
Figure 43. Toggle Mode Function
Rev. A | Page 38 of 44
AD5390/AD5391/AD5392
Power Amplifier Control
Multistage power amplifier designs require a large number of setpoints in the operation and control of the output stage. The AD539x are ideal for these applications because of their small size (LFCSP package) and the integration of 8 and 16 channels, offering 12- and 14-bit resolution. Figure 44 shows a typical transmitter architecture, in which the AD539x DACs can be used in the following control circuits: IBIAS control, average power control (APC), peak power control (PPC), transmit gain control (TGC), and audio level control (ALC). DACs are also required for variable voltage attenuators, phase shifter control, and dc-setpoint control in the overall amplifier design.
PHASE SHIFT
2.5V REFERENCE 2R R VOUT 3 VOUT 0 R 5V RANGE 0.1F
4R 10V RANGE
1/4 OP747/ 1/4 OP4177
R 4R
AD539x-5
VOUT 1 VOUT 4
R 2R
1/4 OP747/ 1/4 OP4177
0V-5V RANGE
0V-10V RANGE
R
1/4 OP747/ 1/4 OP4177
R VOUT 2
I SINK
1/4 OP747/ 1/4 OP4177
IBIAS
R1
Figure 45. Output Configurations for Process Control Applications
Optical Transceivers
AUDIO SOURCE EXCITER POWER AMPLIFIER 50 LOAD
ALC
PPC
APC
TGC
Figure 44. Multistage Power Amplifier Control
Process Control Applications
The AD539x-5 family is ideal for process control applications because it offers a combination of 8 and 16 channels and 12-bit and 14-bit resolution. These applications generally require output voltage ranges of 0 V to 5 V 5 V, 0 V to 10 V 10 V, and current sink and source functions. The AD539x-5 products operate from a single 5 V supply and, therefore, require external signal conditioning to achieve the output ranges described here. Figure 45 shows configurations to achieve these output ranges. The key advantages of using AD539x products in these applications are small package size, pin compatibility with the ability to upgrade from 12 to 14 bits, integrated on-chip 2.5 V reference with 10 ppm/C maximum temperature coefficient, and excellent accuracy specifications. The AD539x family contains an offset and gain register for each channel, so users can perform system-level calibration on a per-channel basis.
The AD539x-3 family of products are ideally suited to optical transceiver applications. In 300 pin MSA applications, for example, digital-to-analog converters are required to control the laser power, APD bias, modulator amplitude and diagnostic information is required as analog outputs from the module. The AD539x offering a combination of 8/16 channels, resolution of 12/14-bits in a 64 lead LFCSP package, operating from a supply voltage of 2.7 V to 5.5 V supply with internal reference and featuring I2C-compatible and SPI interface, make it an ideal component for use in these applications. Figure 46 shows a typical configuration in an optical transceiver application.
3V CONTROLLER SDA SCL I2C BUS PIN/APD AND TIA IRXP
03773-0-032
DVDD SDA SCL
AVDD
VLSRBIAS VLSRPWRMON VXLOPMON
REFOUT/REFIN
AVDD IMODMON 10G LDD AND LASER IMPD IBIASMON TIAs AIN MUX
REFIN
AD539x-3
IBIAS IMOD
12-BIT ADC
AD7994
03773-0-062
Figure 46. Optical Transceiver using the AD539x-3
Rev. A | Page 39 of 44
03773-0-033
AD5390/AD5391/AD5392 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX PIN 1 INDICATOR
49 48
0.60 MAX
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
BOTTOM VIEW
6.35 6.20 SQ* 6.05
0.45 0.40 0.35 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF
33 32
17
16
7.50 REF
1.00 0.85 0.80
12 MAX
* COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION
Figure 47. 64-Lead Lead Frame Chip Scale Package [LFCSP] 9 mm x 9 mm Body (CP-64-2) (Dimensions shown in millimeters)
0.75 0.60 0.45 SEATING PLANE
1.60 MAX
1
12.00 BSC SQ
52 40 39 PIN 1
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
10 6 2
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
VIEW A
13 14 26 27
0.15 0.05
SEATING PLANE
0.65 BSC
0.38 0.32 0.22
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCC
Figure 48. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) (Dimensions shown in millimeters)
Rev. A | Page 40 of 44
AD5390/AD5391/AD5392
ORDERING GUIDE
Model AD5390BCP-3 AD5390BCP-3-REEL AD5390BCP-3-REEL7 AD5390BCP-5 AD5390BCP-5-REEL AD5390BCP-5-REEL7 AD5390BST-3 AD5390BST-3-REEL AD5390BST-5 AD5390BST-5-REEL AD5391BCP-3 AD5391BCP-3-REEL AD5391BCP-3-REEL7 AD5391BCP-5 AD5391BCP-5-REEL AD5391BCP-5-REEL7 AD5391BST-3 AD5391BST-3-REEL AD5391BST-5 AD5391BST-5-REEL AD5392BCP-3 AD5392BCP-3-REEL AD5392BCP-3-REEL7 AD5392BCP-5 AD5392BCP-5-REEL AD5392BCP-5-REEL7 AD5392BST-3 AD5392BST-3-REEL AD5392BST-5 AD5392BST-5-REEL Eval-AD5390EB Eval-AD5391EB Eval-AD5392EB Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Resolution 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit 14-bit AVDD 2.7 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V 4.5 V to 5.5 V 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.5 V 4.5 V to 5.5 V Output Channels 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 Linearity Error (LSBs) 4 4 4 3 3 3 4 4 3 3 1 1 1 1 1 1 1 1 1 1 4 4 4 3 3 3 4 4 3 3 Package Description 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 52-lead LQFP 52-lead LQFP 52-lead LQFP 52-lead LQFP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 52-lead LQFP 52-lead LQFP 52-lead LQFP 52-lead LQFP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 64-lead LFCSP 52-lead LQFP 52-lead LQFP 52-lead LQFP 52-lead LQFP AD5390 Evaluation Board AD5391 Evaluation Board AD5392 Evaluation Board Package Option CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 ST-52 ST-52 ST-52 ST-52 CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 ST-52 ST-52 ST-52 ST-52 CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 CP-64-2 ST-52 ST-52 ST-52 ST-52
Rev. A | Page 41 of 44
AD5390/AD5391/AD5392 NOTES
Rev. A | Page 42 of 44
AD5390/AD5391/AD5392 NOTES
Rev. A | Page 43 of 44
AD5390/AD5391/AD5392 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03773-0--10/04(A)
Rev. A | Page 44 of 44

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